1. Technical Field of the Invention
The present invention relates to the field of integrated circuits provided with an extremely dense interconnection architecture making it possible to increase density on the scale of the elementary cell of an integrated circuit, for example a memory cell of the DRAM or SRAM type.
2. Description of Related Art
U.S. Pat. No. 6,689,655, the disclosure of which is incorporated by reference, describes a method for protecting the gate of a transistor in an integrated circuit, the purpose of which is to produce a connection terminal straddling a transistor gate and the silicon substrate while being insulated from the gate by a nitride layer etched selectively outside the gate zone, so that the connection terminal is in contact with the substrate. The selective etching is obtained by means of a doped polysilicon layer which subsequently is partially etched then insulated by a nitride plug.
The method is relatively complex and difficult to implement. Furthermore, it has been noted that the dopant species implanted in the polysilicon presents a non-negligible risk of diffusion towards other layers.
A need accordingly exists to overcome the drawbacks mentioned above.
More particularly, a need exists to simplify and make more economical the fabrication of a very high-density integrated circuit.